The operating frequencies of semiconductor integrated circuits have become quite high in recent years. For example, an LSI device for a high-speed interface capable of implementing a high-speed serial transfer in the gigabit band includes a serial-to-parallel converter (also referred to as a “DESerializer”) for converting data input serially to parallel data, and a parallel-to-serial converter (also referred to as a “SERializer”) for converting parallel data to serial data. An increase in the degree of integration of semiconductor integrated circuits and the use of multiple channels achieved by high-density packaging have been accompanied by the need for an arrangement in which data on a plurality of channels is received in a short time synchronously between channels. In such an interface, a frame pattern is inserted periodically at prescribed positions in data transmitted serially from the transmitting side, and the frame pattern is detected on the receiving side to assure frame synchronization. It is assumed here that the frame pattern is, e.g., a header byte code (a “comma code”) for byte alignment [see the specification of Japanese Patent Kokai Publication No. JP-A-11-187002 (Patent Reference 1)] and that the timing of byte or word alignment is adjusted appropriately by detection of the comma code.
An arrangement of the kind shown in FIG. 10, for example, is known as an interchannel synchronization device in a terminal that sends and receives data using a plurality of channels [see the specification of Japanese Patent Kokai Publication No. JP-A-5-103031 (Patent Reference 2)]. When one of synchronizing signal detectors 208 to 213 detects a synchronizing signal in this device, a synchronization monitoring unit 214 outputs a timing-signal generation command signal to a first timing signal generator 216, causing the latter to generate a synchronization timing signal, and outputs a changeover command signal to a timing signal changeover unit 218 so that the synchronization timing signal that has been generated will be supplied to the synchronizing signal detector that detected the synchronizing signal. When another synchronizing signal detector detects a synchronizing signal next, a second timing signal generator 217 similarly supplies a synchronization timing signal to this synchronizing signal detector. When synchronization is established on each of these two channels, a delay calculating unit 215 calculates the amount of delay between these two channels and a delay-difference accommodating unit 270 eliminates the difference in delay between the two channels based upon the result of calculation. Whenever a synchronizing signal detector detects a synchronizing signal, a similar operation is repeated until differences in delay among all of the channels are eventually eliminated and all channels are synchronized.
The detecting of channel-to-channel delay and the elimination of this delay in such an arrangement are carried out one after the other in terms of time every two channels in which synchronizing signals are detected. If there are multiple channels, an increase in number of combinations NC2 is attended by the need for a longer period of time to establish synchronization among all channels. This arrangement cannot be applied to a multichannel high-speed interface.
An arrangement having a channel-phase discriminating circuit is known in the art [see the specification of Japanese Patent Kokai Publication No. JP-A-5-30067 (Patent Reference 3)]. A low-speed synchronizing unit having a frame pattern detecting circuit, a frame synchronization/protection circuit and a control circuit for controlling the latter is provided in a number equivalent to the number of receive channels. The discriminating circuit determines whether a frame-pattern detection position detected by each low-speed synchronizing unit or a specific position of a frame has been lost or has occurred owing to a false frame or malfunction of the low-speed synchronizing unit, and estimates the misalignment of channel phase. In FIG. 11, a bit serial-to-parallel converter 1001 corrects the channel phase in a byte serial-to-parallel converter 1002 based upon a channel-shift command from a channel-phase discriminating circuit (which receives frame-position designating signals from low-speed synchronizing units) 1009. Further, when frame synchronization is lost, a bit-shift command is supplied to the bit serial-to-parallel converter 1001 and bit misalignment is corrected. The channel-phase discriminating circuit 1009 discriminates the misalignment of channel phase and the bit serial-to-parallel converter 1001 corrects the misalignment of channel phase. Low-speed synchronizing units 1003, 1004, 1005 and 1006 each have a frame-synchronization detection/protection circuit 1010, a frame pattern detecting circuit 1011 and a control circuit 1012, etc. When frame synchronization is lost, the low-speed synchronizing units 1003, 1004, 1005 and 1006 output bit-shift commands 1040, 1042, 1044 and 1046, respectively.
In the case of the arrangement shown in FIG. 11, the plurality of channels are all compared without performing clock correction on the side of the low-speed synchronizing units 1003, 1004, 1005 and 1006. Control for correcting a delay between channels is complicated. Further, it becomes necessary to correct delay in the interconnection routed to data delay comparison.
In the arrangement shown in FIG. 11, correction of delay is performed after the serial-to-parallel conversion. In a case where the correction of delay is performed before the serial-to-parallel conversion, it is necessary to perform the delay correction before the arrival of the succeeding data in order to achieve implementation of low latency. A pipeline configuration is adopted, etc., and problems arise in terms of high-speed timing design and an increase in power.
[Patent Reference 1]
Japanese Patent Kokai Publication No. JP-A-11-187002
[Patent Reference 2]
Japanese Patent Kokai Publication No. JP-A-5-103031
[Patent Reference 3]
Japanese Patent Kokai Publication No. JP-A-5-30067
[Patent Reference 4]
Japanese Patent Kokai Publication No. JP-P2002-190724A
[Patent Reference 5]
Japanese Patent Kokai Publication No. JP-P2003-333021A
An architecture that is sought in multichannel high-speed interfaces is one that corrects delay (skew) between channels, achieves word synchronization (or frame synchronization) and reduces latency (amount of delay).
The technique described in Patent Reference 2, namely performing synchronization two channels at a time, is such that establishing synchronization on all channels takes time. In terms of latency, therefore, it is difficult to apply this technique to a multichannel high-speed interface.
On the other hand, the technique described in Patent Reference 3 is such that control for correcting delay between channels is complicated and is difficult to apply to a high-speed interface.